Over the past decades, there has been a dramatic increase in functionality and performance of integrated circuits (ICs). This has largely been due to the phenomenon of “scaling”; i.e. component sizes within ICs have been reduced (“scaled”) with every successive generation of technology. Two of the most important components in complementary metal oxide semiconductor (CMOS) ICs are transistors and wires. With “scaling”, transistor density typically improves and this has contributed to the previously-mentioned increases in IC performance and functionality. However, wires (interconnects) that connect together semiconductor devices such as transistors degrade in performance with “scaling”. The situation today is that wires dominate the performance, functionality and power consumption of ICs.
3D stacking of semiconductor devices or chips is one avenue to tackle the wire issues. By arranging transistors in 3 dimensions (3D) instead of 2 dimensions (2D), the transistors in ICs can be placed closer to each other. This reduces wire lengths and keeps wiring delay low. Different techniques exist to construct 3D stacked integrated circuits or chips, including methods based on through-silicon via (TSV) technology and monolithic 3D technology. An example of monolithic 3D ICs is for example disclosed in US20140145272 A1.
However, regardless of the method used, known 3D ICs are essentially individual and distinct 2D transistor layers which are stacked atop one another and which are electronically coupled together by means of interconnects. There is thus still room for methods to provide a deeper integration of transistor layers in 3D ICs.